A study on performances of carrier-based pulse-width modulation techniques for three-phase three-level t-type neutral-point-clamped inverter under switch-open-circuit fault on two neutral-point-connected legs
Multilevel voltage source inverters (VSIs) have been used for several decades thanks to their advantages compared with traditional two level VSI. Among various types of multilevel configuration, the
T-type neutral-point-clamped VSI (3L TNPC VSI or 333-type VSI) has gained the attention in recent
years. Due to the unique structure, the 333-type VSI has critical issues in reliability in operation
such as switch-open-circuit (SOC) and switch-short-circuit (SSC), which lead to several unrequired
issues, for instance, reduction of system performance, distorted and unbalanced output voltages
and currents, or triggering the protection circuits. In some applications, the amplitude reduction
and harmonics distortion of output voltages in SOC faults are not acceptable. Therefore, it is necessary to develop a pulse-width modulation (PWM) algorithm for 333-type VSI working under SOC
fault which guarantees the desired output fundamental component voltage. The simultaneous
SOC fault on two neutral-point-connected legs in the 333-type VSI may cause a large reduction in
the output voltage. Under this circumstance, the 333-type VSI becomes an asymmetrical one called
322-type VSI. Certain studies regarding to the operation of 333-type VSI under SOC faults have been
carried out. However, these studies require more semiconductor devices in order to create a redundant switching circuit. This leads to higher system cost with reduced inverter efficiency due to the
additional loss. In this study, two carrier-based pulse-width modulation (CBPWM) techniques, i.e.
322-sinusoidal PWM (322-SPWM) and 322-medium offset CBPWM (322-MOCBPWM) are proposed
for 322-type VSI. The proposed techniques are firstly simulated in MATLAB/Simulink and then implemented on a hardware setup. Performances of the proposed techniques are evaluated in terms of
total harmonic distortion (THD) and weighted-THD (WTHD) of output voltages. Simulation results
show that considering the worst output voltage under SOC fault, vBC, the proposed 322-SPWM
technique could improve the THD by 40% and the WTHD by 94% compared with the uncompensated case with m=0.8. The corresponding results of 322-MOCBPWM technique are 42% and 96%,
respectively. Characteristics of THD and WTHD values are also presented for demonstration the
effectiveness of the proposed algorithm.
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Tóm tắt nội dung tài liệu: A study on performances of carrier-based pulse-width modulation techniques for three-phase three-level t-type neutral-point-clamped inverter under switch-open-circuit fault on two neutral-point-connected legs
Science & Technology Development Journal – Engineering and Technology, 3(3):472-487 Open Access Full Text Article Research Article Faculty of Electrical and Electronics Engineering, Ho Chi Minh City University of Technology, VNU-HCM Correspondence Nho-Van Nguyen, Faculty of Electrical and Electronics Engineering, Ho Chi Minh City University of Technology, VNU-HCM Email: nvnho@hcmut.edu.vn History Received: 10-01-2020 Accepted: 09-12-2020 Published: 18-12-2020 DOI : 10.32508/stdjet.v3i3.659 Copyright © VNU-HCM Press. This is an open- access article distributed under the terms of the Creative Commons Attribution 4.0 International license. A study on performances of carrier-based pulse-widthmodulation techniques for three-phase three-level t-type neutral-point-clamped inverter under switch-open-circuit fault on two neutral-point-connected legs Phong Nguyen-Hong Le, Nho-Van Nguyen* Use your smartphone to scan this QR code and download this article ABSTRACT Multilevel voltage source inverters (VSIs) have been used for several decades thanks to their advan- tages comparedwith traditional two level VSI. Among various types ofmultilevel configuration, the T-type neutral-point-clamped VSI (3L TNPC VSI or 333-type VSI) has gained the attention in recent years. Due to the unique structure, the 333-type VSI has critical issues in reliability in operation such as switch-open-circuit (SOC) and switch-short-circuit (SSC), which lead to several unrequired issues, for instance, reduction of system performance, distorted and unbalanced output voltages and currents, or triggering the protection circuits. In some applications, the amplitude reduction and harmonics distortion of output voltages in SOC faults are not acceptable. Therefore, it is nec- essary to develop a pulse-width modulation (PWM) algorithm for 333-type VSI working under SOC fault which guarantees the desired output fundamental component voltage. The simultaneous SOC fault on two neutral-point-connected legs in the 333-type VSI may cause a large reduction in the output voltage. Under this circumstance, the 333-type VSI becomes an asymmetrical one called 322-type VSI. Certain studies regarding to the operation of 333-type VSI under SOC faults have been carried out. However, these studies requiremore semiconductor devices in order to create a redun- dant switching circuit. This leads to higher system cost with reduced inverter efficiency due to the additional loss. In this study, two carrier-based pulse-width modulation (CBPWM) techniques, i.e. 322-sinusoidal PWM (322-SPWM) and 322-medium offset CBPWM (322-MOCBPWM) are proposed for 322-type VSI. The proposed techniques are firstly simulated inMATLAB/Simulink and then imple- mented on a hardware setup. Performances of the proposed techniques are evaluated in terms of total harmonic distortion (THD) and weighted-THD (WTHD) of output voltages. Simulation results show that considering the worst output voltage under SOC fault, vBC, the proposed 322-SPWM technique could improve the THD by 40% and the WTHD by 94% compared with the uncompen- sated case with m=0.8. The corresponding results of 322-MOCBPWM technique are 42% and 96%, respectively. Characteristics of THD and WTHD values are also presented for demonstration the effectiveness of the proposed algorithm. Keywords: Carrier-based pulse-width modulation, t-type neutral-point-clamped inverter, switch- open-circuit fault, voltage source inverter, weighted-total harmonic distortion INTRODUCTION Multilevel inverters (MLIs) have been being re- searched for nearly forty years since the first introduc- tion of three-level neutral-point-clamped (3L NPC) voltage source inverter (VSI) in 1981 1,2. Compared with traditional two-level VSI (2L VSI), 3L NPC VSI offers a larger number of benefits. For instance, 3L NPC VSI has lower distortion of output voltage and dv/dt, lower distortion of input current, smaller magnitude of common-mode voltage (CMV) or even elimination of CMV by using some sophisticated modulation methods, and ability in operation with a lower switching frequency 1–7. Among with many types of 3LNPC topology, 3L T-type NPC (3L TNPC) topology has an advantage in terms of efficiency com- pared to 3L NPC 5. For example, 3L TNPC VSI pos- sesses higher efficiency in low-voltage applications for the switching frequency between 4-25 kHz such as photovoltaic (PV) system, uninterruptible power sup- plies (UPSs), and automotive converter system5,8,9. 3L TNPC VSI combines the benefits of both 2L VSI and 3L NPC VSI, such as lower conduction losses, lower switching losses and higher output power qual- ity8. The TNPC topology also allows the usage of lower voltage rating power switches and offers consid- erably power losses comparedwith that of NPC topol- ogy5,8. Cite this article : Le P N, Nguyen N. A study on performances of carrier-based pulse-width modu- lation techniques for thre ... B3, vB3C3, and vC3A3 are the same, at 32%, while under SOC faults with conventional PWM, these values obtained from Figure 11(b) are 194%, 250%, and 170%, respectively. In terms of WTHD, the normal operation values of three L2L voltages are the same, at 0.31% yet under faulty condition, these values are 15.9%, 34.9%, and 15.7%, respectively, are obtained from Figure 12(b). However, with the proposed 322-SPWM technique implemented on the VSI under faulty condition, the harmonic distortion of three output voltages vA3B2, vB2C2, and vC2A3 shown in Figure 11(c) are improved to 69%, 71%, and 64% in terms of THD while the correspondingWTHDs are 0.59%, 0.44%, and 0.59%, respectively, as regards to m=0.5, as shown in Fig- ure 12(c). Simulation and experiment results of output L2L volt- ages and currents in the proposed 322-MOCBPWM 481 Science & Technology Development Journal – Engineering and Technology, 3(3):472-487 Figure 12: Simulated WTHD characteristics of output L2L voltages in SPWM technique: (a) vAB; (b) vBC ; (c) vCA Figure 13: Simulated waveforms of output L2L voltages and currents in MOCBPWM (m=0.8): (a) in pre-fault op- eration with conventional MOCBPWM (333-MOCBPWM); (b) in faulty operation with conventional MOCBPWM; (c) in faulty operation with proposed 322-MOCBPWM. From top to bottom: vAB , vBC , vCA , and iABC . 482 Science & Technology Development Journal – Engineering and Technology, 3(3):472-487 technique are illustrated in the following figures from Figure 13 to Figure 17. The waveforms of output voltages and currents in Figure 13 corresponding to MOCBPWM technique are similar to those of SPWM technique shown inFigure 8. The experiment results in Figure 14 verify the simulation ones. In the simula- tion, THD andWTHD of vA3B2 are 36.4% and 0.28%, respectively while those in experiment are 37.1% and 0.57%, respectively. Similarly, with the 322-MOCBPWM algorithm, output voltages and currents in 322-type VSI are improved, as shown in Figure 15. As an ex- ample for m=0.8, Figure 15(a) and Figure 15(b) show significant increasing in harmonic dis- tortion factor of vAB from THD(vA3B3)=22.5% to THD(vA3B2_0)=63.1%, and from WTHD(vA3B3)=0.14% to WTHD(vA3B2_0)=6.45% , respectively. However, results from Figure 15(c) show that the proposed 322-MOCBPWM technique reduces the THD and WTHD of vAB to 36.4% and 0.28%, respectively, i.e. a reduction of 42% as regards to THD and 96% as regards to WTHD. The fundamental voltage vAB which reduced from 80 V in normal operation to 61.2 V in faulty operation with conventional MOCBPWM, as shown in Figure 15(a) and Figure 15(b), is now recovered to the initial reference value, i.e., VA3B2(1)=80 V which shown in Figure 15(c). The effectiveness of 322-MOCBPWM technique on vBC and vCA can be observed in Figure 15, as well. The simulated THD and WTHD characteristics of output voltages in MOCBPWM technique are illustrated in Figure 16 and Figure 17, respectively. Characteristics shown in Figure 16 and Figure 17 have the similarity to those in Figure 11 and Figure 12 so that the faulty operation of 333-type VSI leads to a considerably surge in harmonic distortion of L2L voltages, especially in the low values of modulation index. In addition, the voltage vBC has the worst harmonic distortion compared to that of vAB and vCA, as regarding to the same value of m. For instance, under faulty condition for m=0.5, THD(vB2C2_0)=285% while THD(vA3B2_0)=194% and THD(vC2A3_0)=170%. With use of the proposed 322-MOCBPWM technique, these values are 72%, 69%, and 64%, respectively. Therefore, there is only small difference between THD values of output voltages with the proposed algorithm. As regarding to WTHD factor, with use of compensating PWM algorithm, at m=1, they are WTHD(vA3B2)=0.29%, WTHD(vB2C2)=0.37%, and WTHD(vC2A3)=0.37% while those values under faulty condition are 4.30%, 4.13%, and 3.58%, respectively. In terms of vBC , simulated results in two CBPWM techniques with m=0.8 can be summarized by Ta- ble 3. Comparison between 322-SPWM technique and 322-MOCBPWM technique, it can be seen that the second one has the lower values of harmonic dis- tortion factors. For instance, under faulty condition, the proposed 322-SPWM strategy has THD(vB2C2) value of 50.1% while that of 322-MOCBPWM strat- egy is 45.7%. The corresponding WTHD(vB2C2) of these algorithms are 0.45% and 0.36%, respectively. Hence, the harmonic distortionmetrics of vBC in 322- MOCBPWM are lower than that in 322-SPWM by 8.8% in terms of THD and by 20% in terms ofWTHD, respectively. CONCLUSION This paper has presented the analysis and imple- mentation of CBPWM techniques on a 333-type VSI working under simultaneous SOC faults on two neutral-point-connected phase-legs. Simulation results show that under the aforementioned SOC fault condition, the output voltages and currents are strongly distorted and unbalanced, with a reduction of fundamental voltages by up to 30%. The use of the proposed 322-SPWMand 322-MOCBPWMtech- niques can help attaining required fundamental volt- ages, and also lowering harmonic content after faulty condition. For the worst harmonic quality voltage vBC , the proposed 322-SPWMhas the ability in reduc- tion of 40% and 94% in terms of THD and WTHD, respectively, while the corresponding results of 322- MOCBPWM technique are 42% and 96%, as regard to m=0.8. The advantages of 322-MOCBPWM tech- nique compared to 322-SPWM technique are also presented, which are not only the extension of mod- ulation range but also the better harmonic quality at the same operating condition. Compared with other studies cited, the proposed techniques do not need any additional hardware but still guarantees the de- sired values of fundamental voltages and balanced output currents. The proposed CBPWM algorithms are simple and easy for implementation, as well. LIST OF ABBREVIATIONS CBPWM: Carrier-based pulse-width modulation SPWM: Sinusoidal pulse-width modulation MOCBPWM: Medium offset carrier-based pulse- width modulation VSI: Voltage source inverter SOC: Switch-open-circuit SSC: Switch-short-circuit THD: Total harmonic distortion UPS: Uninterruptible power supply 483 Science & Technology Development Journal – Engineering and Technology, 3(3):472-487 Figure 14: Experimented waveforms spectra of output L2L voltages and currents of the 322-type VSI with the proposed 322-MOCBPWM (m=0.8): (a) vAB, (b) vBC , (c) vCA , and (d) iABC . X-axis: 5ms/div; Y-axis: 40 V/div (voltages), 1 A/div (currents) 484 Science & Technology Development Journal – Engineering and Technology, 3(3):472-487 Figure15: Simulated spectra of output L2L voltages inMOCBPWM (m=0.8): (a) in pre-fault operationwith conven- tional MOCBPWM (333-MOCBPWM); (b) in faulty operation with conventional MOCBPWM; (c) in faulty operation with proposed 322-MOCBPWM. From top to bottom: vAB, vBC , and vCA . Figure 16: Simulated THD characteristics of output L2L voltages in MOCBPWM technique: (a) vAB ; (b) vBC ; (c) vCA Table 3: Simulated Harmonic Distortion Results Of Vbc (M=0.8) Harmonic distortion metrics Normal operation (with conventional PWM) Faulty operation (with con- ventional PWM) Faulty operation (with pro- posed PWM) 333- SPWM 333- MOCBPWM 333-SPWM 333- MOCBPWM 322-SPWM 322- MOCBPWM THD (%) 24.5 22.5 83.0 80.2 50.1 45.7 WTHD (%) 0.20 0.14 7.54 7.32 0.45 0.36 485 Science & Technology Development Journal – Engineering and Technology, 3(3):472-487 Figure 17: Simulated WTHD characteristics of output L2L voltages in MOCBPWM technique: (a) vAB; (b) vBC ; (c) vCA PV: Photovoltaic WTHD: Weighted-total harmonic distortion 2L VSI: Two-level voltage source inverter 322-type VSI: 322-type asymmetrical voltage source inverter 333-type VSI: Three-level T-type neutral-point clamped voltage source inverter L2L: Line-to-line CONFLICT OF INTERESTS Theauthor declares that there is no conflict of interests regarding the publication of this paper. AUTHORS’ CONTRIBUTIONS Nho-Van Nguyen: Conceptualization, Methodology, Validation, Writing—review and editing, Supervi- sion. Phong Nguyen-Hong Le: Software, Validation, Data curation, Writing—original draft preparation. REFERENCES 1. Nabae A, Takahashi I, Akagi H. A New Neutral-Point-Clamped PWM Inverter. IEEE Transactions on Industry Applications. 1981;IA-17(5):518–523. Available from: https://doi.org/10. 1109/TIA.1981.4503992. 2. Akagi H. Multilevel Converters: Fundamental Circuits and Sys- tems. Proceedings of the IEEE. 2017;105(11):2048–2065. Avail- able from: https://doi.org/10.1109/JPROC.2017.2682105. 3. Rodriguez J, Lai JS, Peng FZ. Multilevel inverters: a survey of topologies, controls, and applications. IEEE Transactions on Industrial Electronics. 2002;49(4):724–738. Available from: https://doi.org/10.1109/TIE.2002.801052. 4. Aly M, Ahmed EM, Shoyama M. Modulation Method for Im- proving Reliability of Multilevel T-Type Inverter in PV Systems. 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IEEE Transactions on Indus- trial Electronics. 2010;57(7):2219–2230. Available from: https: //doi.org/10.1109/TIE.2009.2032430. 13. Holmes DG, Lipo TA. Harmonic Distortion. Pulse Width Modulation for Power Converters: Principles and Practice. 2003;p. 57–94. Available from: https://doi.org/10.1109/ 9780470546284.ch2. 486 Tạp chí Phát triển Khoa học và Công nghệ – Kĩ thuật và Công nghệ, 3(3):472-487 Open Access Full Text Article Bài Nghiên cứu Khoa Điện-Điện tử, Trường Đại học Bách khoa, ĐHQG-HCM Liên hệ Nguyễn Văn Nhờ, Khoa Điện-Điện tử, Trường Đại học Bách khoa, ĐHQG-HCM Email: nvnho@hcmut.edu.vn Lịch sử Ngày nhận: 10-01-2020 Ngày chấp nhận: 09-12-2020 Ngày đăng: 18-12-2020 DOI : 10.32508/stdjet.v3i3.659 Bản quyền © ĐHQG Tp.HCM. Đây là bài báo công bố mở được phát hành theo các điều khoản của the Creative Commons Attribution 4.0 International license. Nghiên cứu kỹ thuật điều chế độ rộng xung sóngmang chomạch nghịch lưu nguồn áp 3 pha 3 bậc TNPC trong điều kiện hởmạch 2 nhánh nối điểm trung tính Lê Nguyễn Hồng Phong, Nguyễn Văn Nhờ* Use your smartphone to scan this QR code and download this article TÓM TẮT Mạch nghịch lưu áp (VSI) đa bậc hiện được sử dụng rộng rãi nhờ vào những ưu điểm so với mạch 2 bậc truyền thống. Trong số các sơ đồ VSI, sơ đồ 3 bậc dạng diode kẹp hình T (3L TNPC VSI hay 333-type VSI) đang ngày càng nhận được sự quan tâm nghiên cứu. Do đặc điểm cấu trúc, mạch 333-type VSI cómột số vấn đề về độ tin cậy khi vận hành, ví dụ như sự cố hởmạch khóa đóng ngắt (SOC) và sự cố ngắn mạch khóa đóng ngắt (SSC), các sự cố này làm giảm hiệu suất hệ thống, gây mất cân bằng và méo dạng điện áp và dòng điện ngõ ra, làm kích hoạt mạch bảo vệ. Trong một số ứng dụng, sự sụt giảm biên độ và méo dạng sóng hài trong điện áp ngõ ra dưới sự cố SOC là không được chấp nhận. Vì vậy, cần phát triểnmột kỹ thuật điều chế độ rộng xung (PWM) chomạch 333-type VSI hoạt động trong điều kiện sự cố SOC để đảm bảo giá trị thành phần cơ bản của điện áp đầu ra theo yêu cầu. Sự cố SOC đồng thời trên 2 nhánh nối điểm trung tính của mạch 333-type VSI dẫn đến sự sụt giảm nghiêm trọng đối với điện áp đầu ra. Trong điều kiện này, mạch 333-type VSI trở thành mạch không đối xứng là 322-type VSI. Nhiều nghiên cứu khác nhau liên quan đến vận hành mạch 333-type VSI trong sự cố SOC đã được tiến hành. Tuy nhiên các nghiên cứu này đều sử dụng thêm linh kiện phần cứng để tạo thànhmột nhánh đóng ngắt bổ sung. Điều này làm tăng chi phí chế tạo và làm giảm hiệu suất của hệ thống do phát sinh thêm tổn hao. Trong bài báo này, hai kỹ thuật PWM sóng mang (CBPWM) được đề xuất cho mạch 322-type VSI, lần lượt là PWM dạng sin (322-SPWM) và CBPWM với hàm offset trung bình (322-MOCBPWM). Các kỹ thuật đề xuất được mô phỏng trước tiên bằng phầnmềmMATLAB/Simulink và sau đó được triển khai trên phần cứng thực nghiệm. Chất lượng kỹ thuật đề xuất được đánh giá qua các chỉ số độ méo dạng sóng hài tổng (THD) và độ méo dạng sóng hài tổng có xét đến trọng số (WTHD) của điện áp ngõ ra. Kết quả mô phỏng cho thấy khi xét điện áp đầu ra vBC là điện áp bị ảnh hưởng nhiều nhất bởi sự cố, tại hệ số điều chế m=0.8 thông số THD và WTHD của kỹ thuật 322-SPWM được giảm với giá trị lần lượt là 40% và 94% so với trường hợp không áp dụng phương pháp đề xuất. Độ giảm tương ứng với kỹ thuật 322-MOCBPWM lần lượt là 42% và 96%. Các đặc tuyến THD và WTHD được trình bày nhằm xác minh tính hiệu quả của phương pháp đề xuất. Từ khoá: mạch nghịch lưu nguồn áp, điều chế độ rộng xung sử dụng sóng mang, mạch nghịch lưu kẹp điểm trung tính kiểu T, sự cố hở mạch khóa đóng ngắt, độ méo dạng sóng hài tổng có xét đến trọng số Trích dẫn bài báo này: Phong L N H, Nhờ N V. Nghiên cứu kỹ thuật điều chế độ rộng xung sóng mang cho mạch nghịch lưu nguồn áp 3 pha 3 bậc TNPC trong điều kiện hở mạch 2 nhánh nối điểm trung tính. Sci. Tech. Dev. J. - Eng. Tech.; 3(3):472-487. 487
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